Digital-to-analog converters have recently seen an increased use of an oversampled architecture. Oversampled digital-to-analog conversion typically runs four, eight or even sixty-four times faster than the input word rate, requiring a corresponding by higher number of samples to be generated for every input sample. Typically, in this type of architecture, digital or discrete-time interpolation is utilized to provide this increase in the input word rate. In digital interpolation, two distinct steps are utilized. The first step of interpolation is to receive the input sequence x[n], representing the Fourier Transform X[f], at a sample rate of f.sub.s. This input sequence x[n] is processed to provide the output sequence y[n], which is essentially the sequence x[n] with M-1 zeroes interspersed between samples, where M is the interpolation factor.
In the frequency domain, the interspersing of zeroes simply rescales the frequency axis. However, the rescaled frequency domain now contains images of the original, low frequency signal. The images can be removed by straightforward, digital low pass filtering, which comprises the second step of the interpolation process. Therefore, the output of the digital low pass filtering step will be the sequence z[n], representing the Fourier Transform Z[f]. The sequence z[n] is the y[n] sequence with the zeroes "filled in". The end result is an interpolator output sequence whose samples occur at a rate that is faster than the input sample rate by a factor of M. The general process of interpolation is disclosed in R. E. Crochiere and L. R. Rabiner, "Interpolation and Decimation of Digital Signals: A Tutorial Review", Proc. IEEE, Vol. 69, pp. 300-331, March 1981, and A. B. Oppenheim and R. W. Schafer, "Discrete-Time Signal Processing", Englewood Cliffs, N.J.: Prentice Hall, 1989. Both of these references are incorporated herein by reference.
The first interpolation step is very conventional and generally comprises the steps of interspersing zeroes between the input samples, which is a relatively straightforward process. However, the second step of digital low pass filtering presents a problem to a hardware designer. Typically, a Finite Impulse Response (FIR) filter of length N is utilized due to the superior phase characteristics and out of band image rejection provided by this type filter. The input to the FIR filter is the y[n] sequence with a second input, the coefficient input, being provided from a storage area that has the coefficients h[0], h1], h2] . . . h[N-1]. This set of filter coefficients completely defines the frequency response of the FIR filter. The number of binary bits required to accurately represent each coefficient is dictated by filter performance parameters, the most sensitive one typically being stop-band rejection. This is disclosed in D. S. K. Chan and L. R. Rabinier, "Analysis of Quantization Errors in the Direct Form for Finite Impulse Response Digital Filters", IEEE Transactions on Audio and Electroacoustics, Vol. AU-21, pp. 354-366, August 1973, which is incorporated herein by reference.
In the case of interpolation, the filter stop-band rejection directly determines the extent to which the out-of-band images will be attenuated. The conventional rule of thumb is about 6 dB of stop-band or image rejection for every binary bit utilized to represent filter coefficients. The conventional filter is realized with a plurality of delay blocks, each having the input multiplied by the associated filter coefficient and then summed, the output rate of the FIR filter being faster than the word rate of the x[n] input sequence by a factor of M. Therefore, the filter must perform N/M multiplies and adds for every output word. Assuming the input data is represented by k binary bits and the FIR filter coefficients are represented by m binary bits, the computational requirement is that at the z[n] output word rate, there are required N/M (k.times.m) multiplies/adds or, that at the x[n] input word rate, there are required N(k.times.m) multiplies/adds. For example, if a 16-bit digital audio data input were interpolated from a word rate of 48 kHz to a rate 4.times. faster, this would result in a word rate of 192 kHz. A digital audio quality FIR filter operating at 4.times. may have a length N=128 with 14-bit coefficients. The resulting computational burden is 128 (16-bit.times.14-bit) multiplies/adds at 48 MHz. Note that the computation rate must double for a stereo implementation and, therefore, a single 16-bit.times.14-bit hardware multiplier must operate at 2.times.28.times.48 KHz=12.28 MHz for digital audio quality 4.times. interpolation.
Since this computation rate is close to the limit for state-of-the-art CMOS technology, and since fast parallel multipliers are too expensive in terms of silicon area to consider utilizing more than one, higher interpolation ratios (M&gt;4) are typically realized in steps. For example, one conventional part number, Part No. SAA7322, manufactured by Philips, provides a stereo CMOS DAC for Compact Discs Digital Audio Systems that realizes a 256.times. interpolation factor in three separate steps: 4.times., 32.times. and 2.times.. The first step of 4.times. is implemented utilizing a multiplier-based 128 tap FIR. The second step of 32.times. is a simple linear interpolator, and the final 2.times. step is a zero-order hold. One can safely draw the general conclusion that although the last steps in a multi-step interpolation process can be quite rudimentary, the need for a fast (parallel) digital multiplier of k-bit input data by m-bit filter coefficients has persisted in conventional, digital audio quality interpolation architectures.
In view of the above disadvantages, there exists a need for an interpolation scheme that provides a relatively high precision FIR filter to result in significant rejection in the stop-band without requiring the expensive and complex multipliers of conventional units.